A nyní nám již systém klíče ukládá do souboru E:\Halda\key.txt, obsah vypadá nějak takto:
Soubor tedy předhodíme Wiresharku, v nastavení vybereme protokol SSL
A máme výsledek, úplně stejné jako při normálním HTTP
root@Jenda:/usr/local/share/openocd# openocd -f interface/altera-usb-blaster.cfg \ > -c "transport select jtag" \ > -f target/stm32f3x.cfgOpen On-Chip Debugger 0.10.0+dev-00362-g78a44055 (2018-03-27-17:48) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html Warn : Adapter driver 'usb_blaster' did not declare which transports it allows; assuming legacy JTAG-only Info : only one transport option; autoselect 'jtag' Warn : Transport "jtag" was already selected jtag adapter speed: 1000 kHz adapter_nsrst_delay: 100 jtag_ntrst_delay: 100 none separate cortex_m reset_config sysresetreq Info : Listening on port 6666 for tcl connections Info : Listening on port 4444 for telnet connections Info : usb blaster interface using libftdi Info : This adapter doesn't support configurable speed Info : JTAG tap: stm32f3x.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) Info : JTAG tap: stm32f3x.bs tap/device found: 0x06422041 (mfg: 0x020 (STMicroelectronics), part: 0x6422, ver: 0x0) Info : stm32f3x.cpu: hardware has 6 breakpoints, 4 watchpoints Info : Listening on port 3333 for gdb connections Info : accepting 'telnet' connection on tcp/4444 Error: Translation from khz to jtag_speed not implemented in procedure 'reset' in procedure 'ocd_bouncer' in procedure 'ocd_process_reset' in procedure 'ocd_process_reset_inner' called at file "embedded:startup.tcl", line 248 in procedure 'stm32f3x.cpu' called at file "embedded:startup.tcl", line 286 in procedure 'ocd_bouncer' Info : JTAG tap: stm32f3x.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x4) Info : JTAG tap: stm32f3x.bs tap/device found: 0x06422041 (mfg: 0x020 (STMicroelectronics), part: 0x6422, ver: 0x0) target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x0800045c msp: 0x20000408 ===== arm v7m registers (0) r0 (/32): 0x00000000 (1) r1 (/32): 0x00000000 (2) r2 (/32): 0x00000000 (3) r3 (/32): 0x00000000 (4) r4 (/32): 0x00000000 (5) r5 (/32): 0x00000000 (6) r6 (/32): 0x00000000 (7) r7 (/32): 0x00000000 (8) r8 (/32): 0x00000000 (9) r9 (/32): 0x00000000 (10) r10 (/32): 0x00000000 (11) r11 (/32): 0x00000000 (12) r12 (/32): 0x00000000 (13) sp (/32): 0x20000408 (14) lr (/32): 0xFFFFFFFF (15) pc (/32): 0x0800045C (16) xPSR (/32): 0x01000000 (17) msp (/32): 0x20000408 (18) psp (/32): 0x00000000 (19) primask (/1): 0x00 (20) basepri (/8): 0x00 (21) faultmask (/1): 0x00 (22) control (/2): 0x00 (23) d0 (/64): 0x0000000000000000 (24) d1 (/64): 0x0000000000000000 (25) d2 (/64): 0x0000000000000000 (26) d3 (/64): 0x0000000000000000 (27) d4 (/64): 0x0000000000000000 (28) d5 (/64): 0x0000000000000000 (29) d6 (/64): 0x0000000000000000 (30) d7 (/64): 0x0000000000000000 (31) d8 (/64): 0x0000000000000000 (32) d9 (/64): 0x0000000000000000 (33) d10 (/64): 0x0000000000000000 (34) d11 (/64): 0x0000000000000000 (35) d12 (/64): 0x0000000000000000 (36) d13 (/64): 0x0000000000000000 (37) d14 (/64): 0x0000000000000000 (38) d15 (/64): 0x0000000000000000 (39) fpscr (/32): 0x00000000 ===== Cortex-M DWT registers (40) dwt_ctrl (/32) (41) dwt_cyccnt (/32) (42) dwt_0_comp (/32) (43) dwt_0_mask (/4) (44) dwt_0_function (/32) (45) dwt_1_comp (/32) (46) dwt_1_mask (/4) (47) dwt_1_function (/32) (48) dwt_2_comp (/32) (49) dwt_2_mask (/4) (50) dwt_2_function (/32) (51) dwt_3_comp (/32) (52) dwt_3_mask (/4) (53) dwt_3_function (/32)
https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_usb_blstr.pdf